The present invention relates generally to voltage dividers and more specifically to a unique voltage divider and its application as a biasing circuit for stacked transistors.
The classic voltage divider is composed of a plurality of resistors connected in series. When the resistors are of equal value, voltage at any node is the ratio of that node number with respect to the total. Thus for example, using two equal resistors, the common node is half the voltage applied across the pair of resistors. One limitation of a resistor divider is that the current which flows through the divider circuit varies directly with the voltage applied to the divider. Thus when the divider is subject to a wide range of voltages, a wide range of currents flows therethrough.
In many applications, there is a need for a divider which carries a current substantially independent of the voltage applied across the divider. Thus resistive voltage dividers cannot meet this requirement.
Thus it is an object of the present invention to provide a voltage divider whose current is substantially independent of the voltage provided across the divider.
These and other objects are achieved by forming the voltage divider wherein the plurality of series connected divider elements each include a depletion mode field effect transistor having its gate and source biased to operate in saturation mode for the operating range of the divider. Preferably the gates and source are connected together. A trimmable resistor is provided in series with the source-drain path of each divider element to adjust the value of the divider element. Also, a resistor may be placed in parallel with the source drain path of the divider element and has a smaller resistance than the output resistance of the transistor to thereby define the output resistance of the divider element. The field effect transistors of the divider operating in the saturation mode have a substantially fixed current compared to resistors for variations in voltage applied.
The voltage divider may be used as a biasing network for stacked transistors. The stacked transistors have their conduction paths connected in series and control terminals connected to the voltage divider. The transistors to be biased may include bipolar transistors having their bases as the control terminals connected to the voltage divider or may be a combination of bipolar and field effect transistors. The bases of adjacent bipolar transistors have a divider transistor connected therebetween. The breakdown voltage of the divider transistors is less than the breakdown voltage of the stacked transistors to provide protection of the stacked transistors. A buffer may be provided between the voltage divider and the control terminal of the stacked transistors. The buffer may be a current follower having its own current source or may be a Darlington amplifier. The buffer may also include a capacitor connected to the voltage divider and the control terminal of the stacked transistor to improve frequency response.
The voltage divider may be used in an operational amplifier having first and second inputs. Each of the inputs includes a plurality of series connected first transistors which are connected to a common voltage divider. A control terminal of one of the first transistors in each of the inputs constitutes the input terminal of the respective input of the amplifier. The amplifier includes a first current source connected in common to the first and second input transistors and a second current source connected in parallel with the first current source. The second current source has the same Idss as that of the divider transistors. Alternatively, the first current source, which is connected in common to the first and second transistors, is connected to the voltage divider by a buffer.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.